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february 2009 rev 1 1/32 AN2829 application note dual step-down controller wit h auxilary voltages for notebook system power introduction the pm6681a is a dual step-down controller with adjustable output voltages that can be used in notebook power systems. this demonstration board represents a typical application circuit. the pm6681a demonstration board allows testing of all functions of the device and provides two switching sections, with (typ.) 1.5 v (out1) and 1.05 v (out2) outputs from 5.5 v to 28 v input battery voltage. the typical operating switching frequency of the two sections is 200 khz/300 khz, respectively. ea ch switching section delivers more than 5 a of output current. an internal linear regulator provides a fixed 5 v output voltage. another internal linear regulator provides an adjustable output voltage (default 3.3 v). both linear regulators can deliver up to 100 ma peak current. figure 1. pm6681a demonstration board am01407v1 www.st.com
contents AN2829 2/32 contents 1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 demonstration board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 demonstration board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 i/o interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 recommended equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 quick start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9 jumper settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 10 feedback output connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 11 test setup and performance summ ary . . . . . . . . . . . . . . . . . . . . . . . . . 18 11.1 test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 11.2 power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 11.3 soft-start and shutdown waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 11.4 1.5 v and 1.05 output efficiency vs. load current . . . . . . . . . . . . . . . . . . . 21 11.5 power consumption analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 11.6 switching frequency vs. load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11.7 linear regulator output voltages vs. output current . . . . . . . . . . . . . . . . . 26 11.8 load transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 12 representative waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
AN2829 list of figures 3/32 list of figures figure 1. pm6681a demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. demonstration board schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. pm6681a demonstration board layout - top layer (pgnd plane and component side) . . . 10 figure 4. pm6681a demonstration board layout - inner layer 1 (sgnd layer and vin plane) . . . . . 10 figure 5. pm6681a demonstration board layout - inner layer 2 (sgnd layer and signals). . . . . . . . 11 figure 6. pm6681a demonstration board layout - bottom layer (pm6681a and component side) . . 11 figure 7. setup connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 8. ref, ldo5 and ldo power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 figure 9. section 1 soft-start waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10. section 2 soft-start waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11. section 1 shutdown waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12. section 2 shutdown waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 13. 1.5 v smps efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 14. 1.05 v smps efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 15. input current vs. input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 16. input current vs. input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 17. input current vs. input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 18. device current consumption vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 19. device current consumption vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 20. 1.5 v output switching frequency vs. load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 21. 1.05 v output switching frequency vs. load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 22. ldo5 output vs. load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 23. adj_ldo load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 24. smps 1.5 v load transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 25. smps 1.05 v load transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 figure 26. smps pulse skip mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 27. smps no-audible skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 28. smps pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
main features AN2829 4/32 1 main features 5.5 v to 36 v input voltage range adjustable output voltages 0.9-3.3 v adjustable ldo delivers 100 ma peak current 5 v ldo delivers 100 ma peak current 1.237 v 1% reference voltage available lossless current sensing using low side mosfet r ds(on) negative current limit soft-start internally fixed at 2 ms soft output discharge latched uvp non-latched ovp selectable pulse skip ping at light loads selectable minimum frequency (33 khz) in pulse skip mode 4 mw maximum quiescent power independent power good signals output voltage ripple compensation.
AN2829 applications 5/32 2 applications notebook, tablet and slate computers mobile system power supplies 3-4 cell li+ battery-powered devices
demonstration board schematic AN2829 6/32 3 demonstration board schematic figure 2. demonstration board schematic diagram am0140 8 v1
AN2829 component list 7/32 4 component list table 1. bill of materials qty component description package part number mfr value 3c1:c3 ceramic capacitor 1812 umk325bj106km-t taiyo-yuden 10 f - 50 v 1c4 ceramic capacitor 1812 nm 10 f - 50 2c5, c6 ceramic capacitor 0805 100 nf - 50 v 1c19 ceramic capacitor 0805 100 nf - 50 v 1c7 poscap capacitor 7343 nm sanyo 2c9, c10 ceramic capacitor 0805 nm 1c11 poscap capacitor 7343 nm sanyo 1c8 poscap capacitor 7343 6tpb330m sanyo 330 f - 12 mr - 6 v 1c12 poscap capacitor 7343 6tpb330m sanyo 330 f - 12 mr - 6 v 2c13, c14 ceramic capacitor 0603 5.6 nf - 50 v 2c15, c16 ceramic capacitor 0603 1 nf - 50 v 2c17, c18 ceramic capacitor 0603 47 pf - 50 v 1c20 ceramic capacitor 0805 1 f - 10 v 1c21 tantalum capacitor 3216 4.7 f - 16 v 1c22 ceramic capacitor 0805 220 nf - 10 v 1c23 ceramic capacitor 0805 10 pf 1cin electrolytic capacitor d=10 mm nm 1 cref ceramic capacitor 0805 100 nf - 50 v 1c26 tantalum capacitor 6032 4.7 f - 35 v
component list AN2829 8/32 1c24, c25 tantalum capacitor 0805 10 f - 6.3 v 1c27 tantalum capacitor 0805 10 f - 6.3 v 1c28 tantalum capacitor 3216 4.7 f - 16 v 1d1 dual schottky diode sot23 bat54a stmicroelectronics 2d2, d3 diode 1 a - 30 v do216aa stps1l30m stmicroelectronics 1ic1 pm6681a device qfn-32 pm6681a stmicroelectronics 1 l1 inductor 1 3 m m x 13 mm mlc1538-152ml coilcraft 1.5 h - 12 a 1 l2 inductor 1 3 m m x 13 mm mlc1515-252ml coilcraf 2.5 h - 8 a 4m1:m4 mosfet control fet so-8 sts12nh3ll 1 r3 resistor 0805 22 k ? - 1% 1 r4 resistor 0805 36 k ? - 1% 1 r5 resistor 0805 3.3 k ? - 1% 1 r6 resistor 0805 3 k ? - 1% 2 r7, r8 resistor 0805 680 ? - 1% 1 r9 resistor 0805 47 ? - 1% 2 r10, r11 resistor 0805 10 ? - 1% 4 r12:r15 resistor 0805 100 k ? - 1% 1 r16 resistor 0805 150 k ? - 1% 1 r17 resistor 0805 560 k ? - 1% 2 r18, r19 resistor 0805 nm 4 r20, r21, r22, r23 resistor 0805 0 ? - 1% 1 r24 resistor 0805 1.1 k ? - 1% 1 r25 resistor 0805 820 ? - 1% 1 r26 resistor 1206 3.9 ? - 1% 1 r27 resistor 0805 10 k ? - 1% 1 r29 resistor 0805 11 k ? - 1% 1 r28 resistor 0805 6.8 k ? - 1% 1 r30 resistor 0805 1.8 k ? - 1% table 1. bill of materials (continued) qty component description package part number mfr value
AN2829 component list 9/32 1 r31 resistor 0603 5.6 k ? - 1% 1 r32 resistor 0603 15 k ? - 1% 1 rld5v, rld3v resistor 0805 nm table 1. bill of materials (continued) qty component description package part number mfr value
demonstration board layout AN2829 10/32 5 demonstration board layout figure 3. pm6681a demonstration board layout - top layer (pgnd plane and component side) figure 4. pm6681a demonstration board layout - inner layer 1 (sgnd layer and v in plane) am01409v1 am01410v1
AN2829 demonstration board layout 11/32 figure 5. pm6681a demonstration board layout - inner layer 2 (sgnd layer and signals) figure 6. pm6681a demonstration board layout - bottom layer (pm6681a and component side) am01411v1 am01412v1
i/o interface AN2829 12/32 6 i/o interface the demonstration board has the following test points: table 2. demonstration board test points test point description v in + input voltage v in - input voltage ground ldo5 5 v linear regulator output ldo_adj adjustable linear regulator output ext5v 5 v external input out1+ out1 switching section output out1- out1 switching section output ground pgood1 out1 switching section power good out2+ out2 switching section output out2+ out2 switching section output ground pgood2 out2 switching section power good j10 junction pin between pgnd and sgnd planes
AN2829 recommended equipment 13/32 7 recommended equipment 5.5 v to 36 v power supply, notebook battery or ac adapter active loads digital multimeters 500 mhz four-trace oscilloscope
quick start AN2829 14/32 8 quick start 1. connect vin+ and vin- test points of the demonstration board to an external power supply. 2. ensure that all switches of dip-switch "s2" are "off". in this condition all outputs are disabled (shutdown-mode). 3. turn "s21"on (shdn pin high). the ld o5 and ldo_adj outputs turn-on (standby- mode). 4. turn "s22" on (en1 pin high). the 1.5 v switching controller brings its output into regulation. the pgood1 pin goes high after soft-start. 5. turn "s23" on (en2 pin high). the 1.05 v switching controller brings its output into regulation. the pgood2 pin goes high after soft-start. 6. in order to load the switching outputs, loads must be connected between the "+" and the "-" output test points, respectively. 7. in order to load the ldo5 linear output, loads must be connected between j10 and ldo5 or resistor rld5v can be mounted on the demonstration board. 8. in order to load the ldo_adj linear output, loads must be connected between j10 and ldo_adj or the alternative resistor r33 can be mounted on the demonstration board.
AN2829 jumper settings 15/32 9 jumper settings it is possible to select different working conditions by using the jumpers: note: please note that jumpers s1, s12 and s13 are already soldered on the demonstration board, and it is not necessary to change them. refer to the schematic to check their proper connection. external bypass connections for the linear regulator ldo5(v5sw) smps frequency selection (fsel) table 3. jumper s11 (connect v5sw pin to s11) position ldo5 working conditions out5v when the main ouput voltage is grea ter than the bootstrap-switchover threshold, an internal 3 ? (max) p-channel mosfet switch connects the v5sw pin to the ldo5 pin, shutting down the ldo5 internal linear regulator. if not used, it must be connected to ground. sgnd the internal linear regulator ldo5 is always on. in this case ldo5 supplies all gate drivers and the internal circuitry. it can provide an output peak current of 100ma. ext5v the internal linear regulator ldo5 remain s off if an alternative 5 v external voltage is applied to the ext5v test-point. an internal 3 ? (max) p-channel mosfet switch connects th e v5sw pin to the ldo5 output. the gate drivers and internal circuitry are supplied by the same 5 v external voltage applied. table 4. jumper s3 (connect fsel pin to s3) position smps out1 smps out2 sgnd 200 khz 325 khz vref 290 khz 425 khz ldo5 390 khz 590 khz
jumper settings AN2829 16/32 smps mode selection (skip) table 5. jumper s10 (connect skip pin to s10) position switching operating mode gnd if the skip pin is tied to ground, pulse-skip mode occurs at light loads. a zero crossing comparator prevent s the inductor current from going negative. vref connecting the skip pin to the vref pin enables pulse skip mode with a minimum switching frequency of appr oximately 25 khz (ultrasonic mode). ldo5 if the skip pin is tied to 5 v, fixed pwm mode occurs. the switching output is in a position to sink and source current from the load.
AN2829 feedback output connections 17/32 10 feedback output connections loop compensation network for very low output voltage ripple. loop compensation network for high output voltage ripple table 6. jumper s4, s5 position output ripple compensation short virtual esr output ripple is generated by using a compensation network connected between the output and the phase pin of the swit ching section. table 7. jumper s8, s9 position feedback connection controller feedback signal connected to the compensation network. table 8. jumper s4, s5 position output ripple compensation open esr output ripple is used. table 9. jumper s8, s9 position feedback connection controller feedback signal connected directly to the output capacitor.
test setup and performance summary AN2829 18/32 11 test setup and performance summary 11.1 test setup the pm6681a demonstration board has the following input/output connections: ? 12 v input through j5-j2 (v in + and v in -) ? 1.5 v smps output through j4-j13 (out1+ and out1-) ? 1.05 v smps output through j1-j12 (out2+ and out2-) ? 3.3 v linear regulator output through ldo_adj - j10 ? 5 v linear regulator output through ldo5 - j3 (ldo5) ? a power supply capable of supplying at least 6 a should be connected to v in +, v in - and two active loads should be connected respectively to out1+, out1- and out2+, out2-. figure 7. setup connections 11.2 power-up as shown in figure 8 , power-up starts when the input voltage is applied and the voltage on the shdn pin is above the device on threshold (1.5 v). first the ldo5 goes up with a masking time of about 4 ms. if the ldo5 output is above the uvlo threshold at this time, the device enters standby mode and the adjustable internal linear regulator ldo is turned on. am0141 3 v1
AN2829 test setup and performance summary 19/32 figure 8. ref, ldo5 and ldo power-up 11.3 soft-start and shutdown waveforms figure 9 , 10 , 11 and 12 show, respectively, the soft-start and shutdown waveforms. the pm681a has an independent internal digital soft-start for each switching section. during the soft-start phase the internal current limit increases from 25% to 100% with steps of 25% to avoid the inductor current rising abruptly. am01414v1
test setup and performance summary AN2829 20/32 figure 9. section 1 soft-start waveforms figure 10. section 2 soft-start waveforms driving the en1, en2 pins below the en off threshold (0.8 v), the switching outputs are connected to ground through an internal 12 ? p-mosfet and are discharged gradually, (discharge mode). when the output voltages reach 0.3 v, the low-side mosfets are turned on, quickly discharging them to ground. am01415v1 out1 i_l en1 am01416v1 out2 i_l en2
AN2829 test setup and performance summary 21/32 figure 11. section 1 shutdown waveforms figure 12. section 2 shutdown waveforms 11.4 1.5 v and 1.05 output efficiency vs. load current figure 13 and 14 show the efficiency versus load current at different input voltage values in pwm mode, skip mode and no audible skip mode. three different input voltages are used: blue: v in =9 v green: v in =12 v red: v in =18 v am01417v1 out1 lg a te1 en1 am0141 8 v1 out2 lg a te2 en2
test setup and performance summary AN2829 22/32 figure 13. 1.5 v smps efficiency figure 14. 1.05 v smps efficiency 11.5 power consumption analysis to measure the consumption of the device in real working conditions, an external power supply of +5 v is connected to ext5v. the two traces on the following figures show the differentiation in the two input currents. once the internal linear regulator is turned on, the device consumption increases. figure 15 shows the input current consumption measured at v in + (including ishdn) and the input device current consumption measured by the vcc pin. both switching sections work in forced pwm mode. no lo ad is applied on the outputs. am01419v1 efficiency v s lo a d c u rrent out1=1,5 v 0 10 20 3 0 40 50 60 70 8 0 90 100 0,001 0,010 0,100 1,000 10,000 lo a d c u rrent [a] efficiency [ % ] s kip na s kip pwm am01420v1 efficiency v s lo a d c u rent out2=1,05 v 0 10 20 3 0 40 50 60 70 8 0 90 100 0,001 0,010 0,100 1,000 10,000 l a od c u rrent [a] efficiency [ % ] s kip na s kip pwm
AN2829 test setup and performance summary 23/32 figure 15. input current vs. input voltage figure 16 shows the input current consumption measured at v in +. both switching sections work in pulse skip mode. no load is applied on the outputs. figure 16. input current vs. input voltage figure 17 shows the input current consumption measured at v in +. both switching sections work in no audible skip mode. no load is applied on the outputs. am01421v1 pwm no lo a d ba ttery c u rrent v s inp u t volt a ge 5.00 10.00 15.00 20.00 25.00 3 0.00 3 5.00 8 10 12 14 16 1 8 20 22 24 26 2 8 inp u t volt a ge [v] inp u t c u rrent [ma] linp u t iext5v am01422v1 s kip no lo a d ba ttery c u rrent v s inp u t volt a ge 0.00 0.10 0.20 0. 3 0 0.40 0.50 0.60 8 10 12 14 16 1 8 20 22 24 26 2 8 inp u t volt a ge [v] inp u t c u rrent [ma] iext5v iinp u t
test setup and performance summary AN2829 24/32 figure 17. input current vs. input voltage in the following figures, the device current consumption is measured in shutdown mode. in shutdown mode all outputs are off (shdn pin low). in standby mode only the linear regulators output are on (v5sw=sgnd ; shdn pin high; en5, en3 pins low). figure 18. device current consumption vs. input voltage am0142 3 v1 no- au di b le s kip no lo a d ba ttery c u rrent v s inp u t volt a ge 1.50 2.00 2.50 3 .00 3 .50 4.00 4.50 8 10 12 14 16 1 8 20 22 24 26 2 8 inp u t volt a ge [v] inp u t c u rrent [ma] iinp u t iext5v am01424v1 s h u tdown mode inp u t ba ttery c u rrent v s inp u t volt a ge 0,00 5,00 10,00 15,00 20,00 25,00 3 0,00 8 10 12 14 16 1 8 20 22 24 26 2 83 0 3 2 3 4 3 6 inp u t volt a ge [v] inp u t c u rrent [ u a]
AN2829 test setup and performance summary 25/32 figure 19. device current consumption vs. input voltage 11.6 switching freque ncy vs. load current figure 20 and 21 show the switching frequency variation with the load current in pwm mode, skip mode and no audible skip mode. 12 v is applied at the v in + and v in - test points. figure 20. 1.5 v output switching frequency vs. load current am01425v1 s t a nd b y mode inp u t ba ttery c u rrent v s inp u t volt a ge 240 260 2 8 0 3 00 3 20 3 40 3 60 38 0 8 10 12 14 16 1 8 20 22 24 26 2 83 0 3 2 3 4 3 6 inp u t volt a ge [v] inp u t c u rrent [ u a] !-v 6switchingfrequencyvsloadcurrent ,oadcurrent;!= 3witchingfrequency;k(z= 3+)0 07- .!3+)0
test setup and performance summary AN2829 26/32 figure 21. 1.05 v output switching frequency vs. load current 11.7 linear regulator output voltages vs. output current figure 22 and 23 show the load regulation respectively for the internal linear regulators ldo5 and the adjustable linear regulator ldo_adj. both switching sections are disabled. 12 v is applied at the v in + and v in - test points. figure 22. ldo5 output vs. load current !-v 6switchingfrequencyvsloadcurrent ,oadcurrent;!= 3witchingfrequency;k(z= 3+)0 07- .!3+)0 am0142 8 v1
AN2829 test setup and performance summary 27/32 figure 23. adj_ldo load regulation 11.8 load transient response the following figures show the load transient response from 1 a to 4 a for both switching outputs. in both cases the pm6681a works in forced pwm mode (the skip pin is high). figure 24. smps 1.5 v load transient response am01429v1 out1 i_l vph as e am014 3 0v1
test setup and performance summary AN2829 28/32 figure 25. smps 1.05 v load transient response am014 3 1v1 out2 i_l vph as e
AN2829 representative waveforms 29/32 12 representative waveforms the following figures show the relevant waveforms of a switching section, to underline the behavior of the device in different working conditions: pulse skip mode, no-audible skip mode and forced pwm mode. figure 26. smps pulse skip mode figure 27. smps no-audible skip mode am014 3 2v1 am014 33 v1
representative waveforms AN2829 30/32 figure 28. smps pwm mode am014 3 4v1
AN2829 revision history 31/32 13 revision history table 10. document revision history date revision changes 25-feb-2009 1 initial release
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